Overall: 1843/3241 fields covered

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL

DR

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle Fields

IDR

Bits 0-31: General-purpose 32-bit data register bits.

CR

Control register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
w
Toggle Fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

REV_IN

Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data.

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

INIT

Initial CRC value

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle Fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle Fields

POL

Bits 0-31: Programmable polynomial.

DBG

0x40015800: Debug support

2/19 fields covered. Toggle Registers

Show register map

IDCODE

MCU Device ID Code Register

Offset: 0x0, reset: 0x0, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle Fields

DEV_ID

Bits 0-11: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

CR

DBG configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_STANDBY
rw 		DBG_STOP
rw
Toggle Fields

DBG_STOP

Bit 1: Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration..

DBG_STANDBY

Bit 2: Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode..

APB_FZ1

DBG APB freeze register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
rw 		DBG_LPTIM2_STOP
rw 		DBG_I2C1_SMBUS_TIMEOUT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM7_STOP
rw 		DBG_TIM6_STOP
rw 		DBG_TIM3_STOP
rw 		DBG_TIM2_STOP
rw
Toggle Fields

DBG_TIM2_STOP

Bit 0: Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted:.

DBG_TIM3_STOP

Bit 1: Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:.

DBG_TIM6_STOP

Bit 4: Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:.

DBG_TIM7_STOP

Bit 5: Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:.

DBG_RTC_STOP

Bit 10: Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:.

DBG_WWDG_STOP

Bit 11: Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:.

DBG_IWDG_STOP

Bit 12: Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:.

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout when core is halted.

DBG_LPTIM2_STOP

Bit 30: Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:.

DBG_LPTIM1_STOP

Bit 31: Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:.

APB_FZ2

DBG APB freeze register 2

Offset: 0xc, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw 		DBG_TIM16_STOP
rw 		DBG_TIM15_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM14_STOP
rw 		DBG_TIM1_STOP
rw
Toggle Fields

DBG_TIM1_STOP

Bit 11: Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:.

DBG_TIM14_STOP

Bit 15: Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:.

DBG_TIM15_STOP

Bit 16: Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx..

DBG_TIM16_STOP

Bit 17: Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:.

DBG_TIM17_STOP

Bit 18: Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:.

DMA1

0x40020000: DMA controller

147/161 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 MAR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 MAR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c MAR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 MAR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 MAR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 MAR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c MAR [7]

ISR

low interrupt status register

Offset: 0x0, reset: 0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle Fields

GIF1

Bit 0: Channel 1 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF1

Bit 1: Channel 1 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF1

Bit 2: Channel 1 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF1

Bit 3: Channel 1 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 4: Channel 2 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF2

Bit 5: Channel 2 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF2

Bit 6: Channel 2 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF2

Bit 7: Channel 2 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 8: Channel 3 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF3

Bit 9: Channel 3 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF3

Bit 10: Channel 3 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF3

Bit 11: Channel 3 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 12: Channel 4 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF4

Bit 13: Channel 4 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF4

Bit 14: Channel 4 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF4

Bit 15: Channel 4 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 16: Channel 5 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF5

Bit 17: Channel 5 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF5

Bit 18: Channel 5 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF5

Bit 19: Channel 5 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 20: Channel 6 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF6

Bit 21: Channel 6 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF6

Bit 22: Channel 6 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF6

Bit 23: Channel 6 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF7

Bit 24: Channel 7 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF7

Bit 25: Channel 7 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF7

Bit 26: Channel 7 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF7

Bit 27: Channel 7 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

high interrupt status register

Offset: 0x4, reset: 0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF7
r 		CHTIF7
r 		CTCIF7
r 		CGIF7
r 		CTEIF6
r 		CHTIF6
r 		CTCIF6
r 		CGIF6
r 		CTEIF5
r 		CHTIF5
r 		CTCIF5
r 		CGIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF15
r 		CHTIF4
r 		CTCIF4
r 		CGIF4
r 		CTEIF3
r 		CHTIF3
r 		CTCIF3
r 		CGIF3
r 		CTEIF2
r 		CHTIF2
r 		CTCIF2
r 		CGIF2
r 		CTEIF1
r 		CHTIF1
r 		CTCIF1
r 		CGIF1
r
Toggle Fields

CGIF1

Bit 0: Clear channel 1 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF1

Bit 1: Clear channel 1 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF1

Bit 2: Clear channel 1 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF1

Bit 3: Clear channel 1 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF2

Bit 4: Clear channel 2 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF2

Bit 5: Clear channel 2 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF2

Bit 6: Clear channel 2 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF2

Bit 7: Clear channel 2 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF3

Bit 8: Clear channel 3 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF3

Bit 9: Clear channel 3 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF3

Bit 10: Clear channel 3 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF3

Bit 11: Clear channel 3 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF4

Bit 12: Clear channel 4 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF4

Bit 13: Clear channel 4 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF4

Bit 14: Clear channel 4 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF15

Bit 15: Clear channel 4 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF5

Bit 16: Clear channel 5 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF5

Bit 17: Clear channel 5 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF5

Bit 18: Clear channel 5 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF5

Bit 19: Clear channel 5 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF6

Bit 20: Clear channel 6 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF6

Bit 21: Clear channel 6 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF6

Bit 22: Clear channel 6 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF6

Bit 23: Clear channel 6 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF7

Bit 24: Clear channel 7 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF7

Bit 25: Clear channel 7 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF7

Bit 26: Clear channel 7 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF7

Bit 27: Clear channel 7 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

DMA channel 1 configuration register

Offset: 0x8, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

DMA channel 1 number of data tegister

Offset: 0xc, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

DMA channel 1 peripheral address

Offset: 0x10, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [1]

DMA channel 1 memory address

Offset: 0x14, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [2]

DMA channel 1 configuration register

Offset: 0x1c, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

DMA channel 1 number of data tegister

Offset: 0x20, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

DMA channel 1 peripheral address

Offset: 0x24, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [2]

DMA channel 1 memory address

Offset: 0x28, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [3]

DMA channel 1 configuration register

Offset: 0x30, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

DMA channel 1 number of data tegister

Offset: 0x34, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

DMA channel 1 peripheral address

Offset: 0x38, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [3]

DMA channel 1 memory address

Offset: 0x3c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [4]

DMA channel 1 configuration register

Offset: 0x44, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

DMA channel 1 number of data tegister

Offset: 0x48, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

DMA channel 1 peripheral address

Offset: 0x4c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [4]

DMA channel 1 memory address

Offset: 0x50, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [5]

DMA channel 1 configuration register

Offset: 0x58, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

DMA channel 1 number of data tegister

Offset: 0x5c, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

DMA channel 1 peripheral address

Offset: 0x60, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [5]

DMA channel 1 memory address

Offset: 0x64, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [6]

DMA channel 1 configuration register

Offset: 0x6c, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [6]

DMA channel 1 number of data tegister

Offset: 0x70, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

DMA channel 1 peripheral address

Offset: 0x74, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [6]

DMA channel 1 memory address

Offset: 0x78, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [7]

DMA channel 1 configuration register

Offset: 0x80, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [7]

DMA channel 1 number of data tegister

Offset: 0x84, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

DMA channel 1 peripheral address

Offset: 0x88, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [7]

DMA channel 1 memory address

Offset: 0x8c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

DMA2

0x40020400: DMA controller

105/115 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 MAR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 MAR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c MAR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 MAR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 MAR [5]

ISR

low interrupt status register

Offset: 0x0, reset: 0, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle Fields

GIF1

Bit 0: Channel 1 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF1

Bit 1: Channel 1 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF1

Bit 2: Channel 1 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF1

Bit 3: Channel 1 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 4: Channel 2 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF2

Bit 5: Channel 2 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF2

Bit 6: Channel 2 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF2

Bit 7: Channel 2 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 8: Channel 3 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF3

Bit 9: Channel 3 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF3

Bit 10: Channel 3 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF3

Bit 11: Channel 3 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 12: Channel 4 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF4

Bit 13: Channel 4 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF4

Bit 14: Channel 4 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF4

Bit 15: Channel 4 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 16: Channel 5 global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF5

Bit 17: Channel 5 transfer complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF5

Bit 18: Channel 5 half transfer flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF5

Bit 19: Channel 5 transfer error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

high interrupt status register

Offset: 0x4, reset: 0, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF5
r 		CHTIF5
r 		CTCIF5
r 		CGIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF15
r 		CHTIF4
r 		CTCIF4
r 		CGIF4
r 		CTEIF3
r 		CHTIF3
r 		CTCIF3
r 		CGIF3
r 		CTEIF2
r 		CHTIF2
r 		CTCIF2
r 		CGIF2
r 		CTEIF1
r 		CHTIF1
r 		CTCIF1
r 		CGIF1
r
Toggle Fields

CGIF1

Bit 0: Clear channel 1 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF1

Bit 1: Clear channel 1 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF1

Bit 2: Clear channel 1 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF1

Bit 3: Clear channel 1 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF2

Bit 4: Clear channel 2 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF2

Bit 5: Clear channel 2 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF2

Bit 6: Clear channel 2 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF2

Bit 7: Clear channel 2 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF3

Bit 8: Clear channel 3 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF3

Bit 9: Clear channel 3 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF3

Bit 10: Clear channel 3 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF3

Bit 11: Clear channel 3 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF4

Bit 12: Clear channel 4 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF4

Bit 13: Clear channel 4 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF4

Bit 14: Clear channel 4 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF15

Bit 15: Clear channel 4 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF5

Bit 16: Clear channel 5 global interrupt flag.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF5

Bit 17: Clear channel 5 transfer complete flag.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF5

Bit 18: Clear channel 5 half transfer flag.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF5

Bit 19: Clear channel 5 transfer error flag.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

DMA channel 1 configuration register

Offset: 0x8, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

DMA channel 1 number of data tegister

Offset: 0xc, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

DMA channel 1 peripheral address

Offset: 0x10, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [1]

DMA channel 1 memory address

Offset: 0x14, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [2]

DMA channel 1 configuration register

Offset: 0x1c, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

DMA channel 1 number of data tegister

Offset: 0x20, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

DMA channel 1 peripheral address

Offset: 0x24, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [2]

DMA channel 1 memory address

Offset: 0x28, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [3]

DMA channel 1 configuration register

Offset: 0x30, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

DMA channel 1 number of data tegister

Offset: 0x34, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

DMA channel 1 peripheral address

Offset: 0x38, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [3]

DMA channel 1 memory address

Offset: 0x3c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [4]

DMA channel 1 configuration register

Offset: 0x44, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

DMA channel 1 number of data tegister

Offset: 0x48, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

DMA channel 1 peripheral address

Offset: 0x4c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [4]

DMA channel 1 memory address

Offset: 0x50, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

CR [5]

DMA channel 1 configuration register

Offset: 0x58, reset: 0, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripherarl increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

DMA channel 1 number of data tegister

Offset: 0x5c, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

DMA channel 1 peripheral address

Offset: 0x60, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR [5]

DMA channel 1 memory address

Offset: 0x64, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields

MA

Bits 0-31: Memory address.

DMAMUX

0x40020800: DMAMUX

11/91 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 C0CR
0x4 C1CR
0x8 C2CR
0xc C3CR
0x10 C4CR
0x14 C5CR
0x18 C6CR
0x80 CSR
0x84 CFR
0x100 RG0CR
0x104 RG1CR
0x108 RG2CR
0x10c RG3CR
0x140 RGSR
0x144 RGCFR

C0CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

C1CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

C2CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

C3CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0xc, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

C4CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x10, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

C5CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

C6CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

CSR

DMAMUX request line multiplexer interrupt channel status register

Offset: 0x80, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF6
r 		SOF5
r 		SOF4
r 		SOF3
r 		SOF2
r 		SOF1
r 		SOF0
r
Toggle Fields

SOF0

Bit 0: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF1

Bit 1: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF2

Bit 2: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF3

Bit 3: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF4

Bit 4: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF5

Bit 5: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF6

Bit 6: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

CFR

DMAMUX request line multiplexer interrupt clear flag register

Offset: 0x84, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF6
w 		CSOF5
w 		CSOF4
w 		CSOF3
w 		CSOF2
w 		CSOF1
w 		CSOF0
w
Toggle Fields

CSOF0

Bit 0: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF1

Bit 1: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF2

Bit 2: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF3

Bit 3: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF4

Bit 4: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF5

Bit 5: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF6

Bit 6: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

RG0CR

DMAMUX request generator channel x configuration register

Offset: 0x100, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

RG1CR

DMAMUX request generator channel x configuration register

Offset: 0x104, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

RG2CR

DMAMUX request generator channel x configuration register

Offset: 0x108, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

RG3CR

DMAMUX request generator channel x configuration register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

RGSR

DMAMUX request generator interrupt status register

Offset: 0x140, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF3
r 		OF2
r 		OF1
r 		OF0
r
Toggle Fields

OF0

Bit 0: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

OF1

Bit 1: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

OF2

Bit 2: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

OF3

Bit 3: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

RGCFR

DMAMUX request generator interrupt clear flag register

Offset: 0x144, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF3
w 		COF2
w 		COF1
w 		COF0
w
Toggle Fields

COF0

Bit 0: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

COF1

Bit 1: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

COF2

Bit 2: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

COF3

Bit 3: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

GPIOA

0x50000000: General-purpose I/Os

161/177 fields covered. Toggle Registers

Show register map

MODER

GPIO port mode register

Offset: 0x0, reset: 0xEBFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, reset: 0x24000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOB

0x50000400: General-purpose I/Os

161/177 fields covered. Toggle Registers

Show register map

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOC

0x50000800: General-purpose I/Os

161/177 fields covered. Toggle Registers

Show register map

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOD

0x50000c00: General-purpose I/Os

161/177 fields covered. Toggle Registers

Show register map

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOE

0x50001000: General-purpose I/Os

161/177 fields covered. Toggle Registers

Show register map

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOF

0x50001400: General-purpose I/Os

161/177 fields covered. Toggle Registers

Show register map

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

I2C1

0x40005400: Inter-integrated circuit

76/76 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle Fields

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: Stop detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle Fields

SADD

Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect..

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle Fields

OA1

Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle Fields

OA2

Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle Fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle Fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle Fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle Fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C2

0x40005800: Inter-integrated circuit

76/76 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle Fields

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: Stop detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle Fields

SADD

Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect..

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle Fields

OA1

Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle Fields

OA2

Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle Fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle Fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle Fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle Fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

IWDG

0x40003000: Independent watchdog

7/7 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 KR
0x4 PR
0x8 RLR
0xc SR
0x10 WINR

KR

Key register

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PR

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle Fields

PR

Bits 0-2: Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset..

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLR

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle Fields

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0x0-0xfff

SR

Status register

Offset: 0xc, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle Fields

PVU

Bit 0: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset..

RVU

Bit 1: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset..

WVU

Bit 2: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset..

WINR

Window register

Offset: 0x10, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle Fields

WIN

Bits 0-11: Watchdog counter window value.

Allowed values: 0x0-0xfff

TIM1

0x40012c00: Advanced-timers

32/190 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 AF1
0x64 AF2
0x68 TISEL

CR1

control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT..

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS2

Bit 10: Output Idle state 2 (OC2 output) Refer to OIS1 bit.

OIS2N

Bit 11: Output Idle state 2 (OC2N output) Refer to OIS1N bit.

OIS3

Bit 12: Output Idle state 3 (OC3 output) Refer to OIS1 bit.

OIS3N

Bit 13: Output Idle state 3 (OC3N output) Refer to OIS1N bit.

OIS4

Bit 14: Output Idle state 4 (OC4 output) Refer to OIS1 bit.

OIS5

Bit 16: Output Idle state 5 (OC5 output) Refer to OIS1 bit.

OIS6

Bit 18: Output Idle state 6 (OC6 output) Refer to OIS1 bit.

MMS2

Bits 20-23: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

SMCR

slave mode control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw 		SMS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS1
rw 		OCCS
rw 		SMS1
rw
Toggle Fields

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

OCCS

Bit 3: OCREF clear selection This bit is used to select the OCREF clear source..

TS1

Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/slave mode.

ETF

Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

ETPS

Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..

ECE

Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

ETP

Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

1/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

CC2IF

Bit 2: Capture/Compare 2 interrupt flag Refer to CC1IF description.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag Refer to CC1IF description.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag Refer to CC1IF description.

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software..

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

B2IF

Bit 8: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

CC2OF

Bit 10: Capture/Compare 2 overcapture flag Refer to CC1OF description.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag Refer to CC1OF description.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag Refer to CC1OF description.

SBIF

Bit 13: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation..

CC5IF

Bit 16: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output).

CC6IF

Bit 17: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output).

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CC2G

Bit 2: Capture/Compare 2 generation Refer to CC1G description.

CC3G

Bit 3: Capture/Compare 3 generation Refer to CC1G description.

CC4G

Bit 4: Capture/Compare 4 generation Refer to CC1G description.

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output..

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

B2G

Bit 8: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER)..

IC2PSC

Bits 10-11: Input capture 2 prescaler Refer to IC1PSC[1:0] description..

IC2F

Bits 12-15: Input capture 2 filter Refer to IC1F[3:0] description..

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

2/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M1
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M1

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER)..

OC2FE

Bit 10: Output Compare 2 fast enable Refer to OC1FE description..

OC2PE

Bit 11: Output Compare 2 preload enable Refer to OC1PE description..

OC2M

Bits 12-14: Output Compare 2 mode Refer to OC1M[3:0] description..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output Compare 2 clear enable Refer to OC1CE description..

OC1M2

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..

OC2M_3

Bit 24: Output Compare 2 mode Refer to OC1M[3:0] description..

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (output mode)

Offset: 0x1c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle Fields

CC3S

Bits 0-1: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER)..

IC3PSC

Bits 2-3: Input capture 3 prescaler Refer to IC1PSC[1:0] description..

IC3F

Bits 4-7: Input capture 3 filter Refer to IC1F[3:0] description..

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER)..

IC4PSC

Bits 10-11: Input capture 4 prescaler Refer to IC1PSC[1:0] description..

IC4F

Bits 12-15: Input capture 4 filter Refer to IC1F[3:0] description..

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER)..

OC3FE

Bit 2: Output compare 3 fast enable Refer to OC1FE description..

OC3PE

Bit 3: Output compare 3 preload enable Refer to OC1PE description..

OC3M

Bits 4-6: Output compare 3 mode Refer to OC1M[3:0] description..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable Refer to OC1CE description..

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER)..

OC4FE

Bit 10: Output compare 4 fast enable Refer to OC1FE description..

OC4PE

Bit 11: Output compare 4 preload enable Refer to OC1PE description..

OC4M

Bits 12-14: Output compare 4 mode Refer to OC3M[3:0] description..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable Refer to OC1CE description..

OC3M_3

Bit 16: Output compare 3 mode Refer to OC1M[3:0] description..

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output compare 4 mode Refer to OC3M[3:0] description..

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC2E

Bit 4: Capture/Compare 2 output enable Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output polarity Refer to CC1P description.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable Refer to CC1NE description.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity Refer to CC1NP description.

CC3E

Bit 8: Capture/Compare 3 output enable Refer to CC1E description.

CC3P

Bit 9: Capture/Compare 3 output polarity Refer to CC1P description.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable Refer to CC1NE description.

CC3NP

Bit 11: Capture/Compare 3 complementary output polarity Refer to CC1NP description.

CC4E

Bit 12: Capture/Compare 4 output enable Refer to CC1E description.

CC4P

Bit 13: Capture/Compare 4 output polarity Refer to CC1P description.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity Refer to CC1NP description.

CC5E

Bit 16: Capture/Compare 5 output enable Refer to CC1E description.

CC5P

Bit 17: Capture/Compare 5 output polarity Refer to CC1P description.

CC6E

Bit 20: Capture/Compare 6 output enable Refer to CC1E description.

CC6P

Bit 21: Capture/Compare 6 output polarity Refer to CC1P description.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0..

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”)..

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-15: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields

REP

Bits 0-15: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0x0-0xffff

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields

CCR2

Bits 0-15: Capture/Compare 2 value.

Allowed values: 0x0-0xffff

CCR3

capture/compare register 3

Offset: 0x3c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle Fields

CCR3

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle Fields

CCR4

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

3/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle Fields

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tDTG with tDTG=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtDTG with tDTG=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtDTG with tDTG=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtDTG with tDTG=16xtDTS. Example if tDTS=125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A)..

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2F

Bits 20-23: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2E

Bit 24: Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BK2P

Bit 25: Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BK2DSRM

Bit 27: Break2 Disarm Refer to BKDSRM description.

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BK2BID

Bit 29: Break2 bidirectional Refer to BKBID description.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields

DBA

Bits 0-4: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....

DBL

Bits 8-12: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA..

DMAR

DMA address for full transfer

Offset: 0x4c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields

DMAB

Bits 0-31: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

OR1

option register 1

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCREF_CLR
rw
Toggle Fields

OCREF_CLR

Bit 0: Ocref_clr source selection This bit selects the ocref_clr input source..

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_3
rw 		OC5M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle Fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register 4

Offset: 0x58, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle Fields

CCR5

Bits 0-15: Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output..

GC5C1

Bit 29: Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..

GC5C2

Bit 30: Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..

GC5C3

Bit 31: Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals..

CCR6

capture/compare register 4

Offset: 0x5c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle Fields

CCR6

Bits 0-15: Capture/Compare value.

AF1

DMA address for full transfer

Offset: 0x60, reset: 0x00000001, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle Fields

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

ETRSEL

Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

AF2

DMA address for full transfer

Offset: 0x64, reset: 0x00000001, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle Fields

BK2INE

Bit 0: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2CMP1E

Bit 1: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2CMP2E

Bit 2: BRK2 COMP2 enable This bit enables the COMP2 for the timer’s BRK2 input. COMP2 output is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2INP

Bit 9: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

TISEL

TIM1 timer input selection register

Offset: 0x68, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw 		TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle Fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input Others: Reserved.

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input Others: Reserved.

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input Others: Reserved.

TIM14

0x40002000: General purpose timers

11/31 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x68 TISEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=’0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w 		UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

OC1FE

Bit 2: Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_3

Bit 16: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable..

CC1P

Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..

CC1NP

Bit 3: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description)..

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-15: low counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-15: Low Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields

CCR1

Bits 0-15: Low Capture/Compare 1 value.

TISEL

TIM timer input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle Fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TIM15

0x40014000: General purpose timers

13/97 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x44 BDTR
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx).

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..

OIS2

Bit 10: Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register)..

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw 		SMS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS1
rw 		SMS1
rw
Toggle Fields

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS1

Bits 4-6: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/slave mode.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

CC2IF

Bit 2: Capture/Compare 2 interrupt flag refer to CC1IF description.

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software..

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

CC2OF

Bit 10: Capture/Compare 2 overcapture flag Refer to CC1OF description.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
rw 		CC2G
w 		CC1G
w 		UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CC2G

Bit 2: Capture/Compare 2 generation Refer to CC1G description.

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER)..

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1M1
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M1

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER)..

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC1M2

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..

OC2M_3

Bit 24: Output Compare 2 mode.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC2E

Bit 4: Capture/Compare 2 output enable Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output polarity Refer to CC1P description.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity Refer to CC1NP description.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields

CCR2

Bits 0-15: Capture/Compare 2 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle Fields

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818)..

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....

DMAR

DMA address for full transfer

Offset: 0x4c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM15 alternate register 1

Offset: 0x60, reset: 0x00000001, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle Fields

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle Fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input Others: Reserved.

TIM16

0x40014400: General purpose timers

12/66 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software..

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_3

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16..

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle Fields

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....

DMAR

DMA address for full transfer

Offset: 0x4c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM17 option register 1

Offset: 0x60, reset: 0x00000001, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle Fields

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle Fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TIM17

0x40014800: General purpose timers

12/66 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software..

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_3

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16..

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle Fields

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....

DMAR

DMA address for full transfer

Offset: 0x4c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM17 option register 1

Offset: 0x60, reset: 0x00000001, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle Fields

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle Fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TIM3

0x40000400: General-purpose-timers

20/115 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x24 CNT_ALTERNATE5
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 AF1
0x68 TISEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle Fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw 		SMS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS1
rw 		OCCS
rw 		SMS1
rw
Toggle Fields

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

OCCS

Bit 3: OCREF clear selection This bit is used to select the OCREF clear source.

TS1

Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

ETPS

Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..

ECE

Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

ETP

Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

CC2IF

Bit 2: Capture/Compare 2 interrupt flag Refer to CC1IF description.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag Refer to CC1IF description.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag Refer to CC1IF description.

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

CC2OF

Bit 10: Capture/compare 2 overcapture flag refer to CC1OF description.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag refer to CC1OF description.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag refer to CC1OF description.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CC2G

Bit 2: Capture/compare 2 generation Refer to CC1G description.

CC3G

Bit 3: Capture/compare 3 generation Refer to CC1G description.

CC4G

Bit 4: Capture/compare 4 generation Refer to CC1G description.

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable..

CC1P

Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..

CC1NP

Bit 3: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description..

CC2E

Bit 4: Capture/Compare 2 output enable. Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output Polarity. refer to CC1P description.

CC2NP

Bit 7: Capture/Compare 2 output Polarity. Refer to CC1NP description.

CC3E

Bit 8: Capture/Compare 3 output enable. Refer to CC1E description.

CC3P

Bit 9: Capture/Compare 3 output Polarity. Refer to CC1P description.

CC3NP

Bit 11: Capture/Compare 3 output Polarity. Refer to CC1NP description.

CC4E

Bit 12: Capture/Compare 4 output enable. refer to CC1E description.

CC4P

Bit 13: Capture/Compare 4 output Polarity. Refer to CC1P description.

CC4NP

Bit 15: Capture/Compare 4 output Polarity. Refer to CC1NP description.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle Fields

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value (TIM2 only).

CNT_ALTERNATE5

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw 		CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-30: Most significant part counter value (TIM2) nullLeast significant part of counter value.

UIFCPY

Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-31: High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields

CCR1

Bits 0-31: High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed..

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields

CCR2

Bits 0-31: High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed..

CCR3

capture/compare register 3

Offset: 0x3c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle Fields

CCR3

Bits 0-31: High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed..

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle Fields

CCR4

Bits 0-31: High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed..

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields

DBA

Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....

DMAR

DMA address for full transfer

Offset: 0x4c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM option register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCREF_CLR
rw
Toggle Fields

OCREF_CLR

Bit 0: Ocref_clr source selection This bit selects the ocref_clr input source..

AF1

TIM alternate function option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle Fields

ETRSEL

Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved.

TISEL

TIM alternate function option register 1

Offset: 0x68, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle Fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.

TIM6

0x40001000: Basic timers

14/15 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields

MMS

Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

TIM7

0x40001400: Basic timers

14/15 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields

MMS

Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields

ARR

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

53/170 fields covered. Toggle Registers

Show register map

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_FIFO_ENABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXFNFIE
rw 		TCIE
rw 		RXFNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

Baud rate register

Offset: 0xc, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle Fields

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1c, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

ISR_FIFO_ENABLED

Interrupt & status register

Offset: 0x1c, reset: 0x008000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXFNF
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

53/170 fields covered. Toggle Registers

Show register map

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_FIFO_ENABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXFNFIE
rw 		TCIE
rw 		RXFNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

Baud rate register

Offset: 0xc, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle Fields

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1c, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

ISR_FIFO_ENABLED

Interrupt & status register

Offset: 0x1c, reset: 0x008000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXFNF
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

53/170 fields covered. Toggle Registers

Show register map

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_FIFO_ENABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXFNFIE
rw 		TCIE
rw 		RXFNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

Baud rate register

Offset: 0xc, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle Fields

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1c, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

ISR_FIFO_ENABLED

Interrupt & status register

Offset: 0x1c, reset: 0x008000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXFNF
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

USART4

0x40004c00: Universal synchronous asynchronous receiver transmitter

53/170 fields covered. Toggle Registers

Show register map

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_FIFO_ENABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXFNFIE
rw 		TCIE
rw 		RXFNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

Baud rate register

Offset: 0xc, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle Fields

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1c, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

ISR_FIFO_ENABLED

Interrupt & status register

Offset: 0x1c, reset: 0x008000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXFNF
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

USART5

0x40005000: Universal synchronous asynchronous receiver transmitter

53/170 fields covered. Toggle Registers

Show register map

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_FIFO_ENABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXFNFIE
rw 		TCIE
rw 		RXFNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

Baud rate register

Offset: 0xc, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle Fields

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1c, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

ISR_FIFO_ENABLED

Interrupt & status register

Offset: 0x1c, reset: 0x008000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXFNF
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

USART6

0x40013c00: Universal synchronous asynchronous receiver transmitter

53/170 fields covered. Toggle Registers

Show register map

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_FIFO_ENABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXFNFIE
rw 		TCIE
rw 		RXFNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

Baud rate register

Offset: 0xc, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle Fields

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1c, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

ISR_FIFO_ENABLED

Interrupt & status register

Offset: 0x1c, reset: 0x008000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXFNF
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

VREFBUF

0x40010030: System configuration controller

1/5 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR

CSR

VREFBUF control and status register

Offset: 0x0, reset: 0x00000002, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r 		VRS
rw 		HIZ
rw 		ENVR
rw
Toggle Fields

ENVR

Bit 0: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode..

HIZ

Bit 1: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration..

VRS

Bit 2: Voltage reference scale This bit selects the value generated by the voltage reference buffer..

VRR

Bit 3: Voltage reference buffer ready.

CCR

VREFBUF calibration control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle Fields

TRIM

Bits 0-5: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows the tuning of the internal reference buffer voltage..

WWDG

0x40002c00: System window watchdog

6/6 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFR
0x8 SR

CR

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle Fields

T

Bits 0-6: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)..

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGAÂ =Â 1, the watchdog can generate a reset..

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTB
rw 		EWI
rw 		W
rw
Toggle Fields

W

Bits 0-6: 7-bit window value These bits contain the window value to be compared with the down-counter..

Allowed values: 0x0-0x7f

EWI

Bit 9: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset..

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

WDGTB

Bits 11-13: Timer base The timebase of the prescaler can be modified as follows:.

Allowed values:
4: Div16: Counter clock (PCLK1 div 4096) div 16
5: Div32: Counter clock (PCLK1 div 4096) div 32
6: Div64: Counter clock (PCLK1 div 4096) div 64
7: Div128: Counter clock (PCLK1 div 4096) div 128
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

SR

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced